hs – -Translation – Keybot Dictionary

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  Lead-Free and RoHS Summ...  
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PBGA-HS
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PDIP
  MAX115 2x4-Channel, Sim...  
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The MAX115/MAX116 are high-speed, multichannel, 12-bit data-acquisition systems (DAS) with simultaneous track/holds (T/Hs). These devices contain a 12-bit, 2µs, successive-approximation analog-to-digital converter (ADC), a +2.5V reference, a buffered reference input, and a bank of four simultaneous-sampling T/H amplifiers that preserve the relative phase information of the sampled inputs.
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MAX115/MAX116は、同時トラック/ホールド(T/H)を備えた、高速、マルチチャネル、12ビットのデータ収集システム(DAS)です。これらのデバイスには、12ビット、2µsの逐次比較型アナログ-ディジタルコンバータ(ADC)、+2.5Vリファレンス、バッファ付リファレンス入力、および(サンプリングされた入力の相対位相情報を保持する) 4つの同時サンプリングT/Hアンプのバンクを内蔵しています。いずれも各T/H用に2つのマルチプレクス入力を備え、合計8つの入力に対応できます。加えて、コンバータは±17Vまでの過電圧に耐えるため、どのチャネルにフォルト条件が発生しても、ICが損傷を受けることはありません。入力範囲は±5V (MAX115)および±2.5V (MAX116)です。
  Understanding Pipelined...  
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The front-end S&Hs and DAC actually need about 12-bit accuracy, whereas the components in subsequent stages require less accuracy (for example, 10-bit accuracy for Stage 2, 8-bit for Stage 3, and so forth).
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The MAX1200 (16-bit, 1Msps), MAX1201 (14-bit 2Msps), and MAX1205 (14-bit, 1Msps) family¹ of ADCs employs digital calibration to ensure excellent accuracy and dynamic performance. Each device is a CMOS pipelined ADC with four 4-bit stages (with 1-bit overlap) and a 5-bit flash ADC at the end, giving a total of 3 + 3 + 3 + 3 + 5 = 17 raw bits (see Figure 3). The extra one to three bits are required by the digital calibration to quantize the error terms to greater accuracy than the ADC itself; the extra bits are also discarded to give either 14 bits or 16 bits overall.